An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links

Abstract

In this paper; we present a BIST scheme for on-chip short-time interval measurement intended for characterizing the time-domain specijications, e.g., the rise/fall time of modern high-speed communication transceivers. To reduce hardware overhead, the proposed BIST technique uses the coherent under-sampling principle, and measures implicitly the time interval in a two-pass manner: Simulation results are shown to validate the proposed technique.

DOI: 10.1109/VTS.2001.923466

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Cite this paper

@inproceedings{Huang2001AnOS, title={An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links}, author={Jiun-Lang Huang and Kwang-Ting Cheng}, booktitle={VTS}, year={2001} }