An MDE-based approach to the verification of SysML state machine diagram

@inproceedings{Huang2012AnMA,
  title={An MDE-based approach to the verification of SysML state machine diagram},
  author={Xiaopu Huang and Qingqing Sun and Jiangwei Li and Minxue Pan and Tian Zhang},
  booktitle={Internetware},
  year={2012}
}
State Machine Diagram (SMD) is one of the SysML behavior diagrams, but it is a kind of semi-formal model language. As a consequence, models can not be verified conveniently and efficiently, especially in real-time embedded system (RTES) field as there are no descriptions of time and probability in SMD. To address these problems, we extend SMD with time and… CONTINUE READING