• Corpus ID: 30486542

An Integrated Switching Technique for Minimizing Power Consumption Using MDFSD in Domino Logic System

  title={An Integrated Switching Technique for Minimizing Power Consumption Using MDFSD in Domino Logic System},
  author={Jagan Muralidharan and Dr. P. Mamimegalai},
A domino logic technique is designed to meet the critical concern of the VLSI era with convenience and high microelectronic devices, power consumption of the digital circuit. The design and circuit performance improves the power consumption, area and delay of the circuit. If there is a path delay in wide fan multiplexers, then path reads out becomes more difficult and there is high power consumption due to switching activity, also it has high noise immunity in the dynamic gates. At a lower… 
1 Citations
Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progression and Low Power Alleviation
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Energy-Efficient Noise-Tolerant Dynamic Styles for
A new high-speed Domino circuit, called HS-Domino has been developed, which extends Domino's operation in the deep submicron regime while dissipating low dynamic power with minimal area over- head.
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High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
  • M. Allam, M. Anis, M. Elmasry
  • Engineering
    ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)
  • 2000
A new high-speed domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-off between performance and noise margins in conventional CD-Domino logic while dissipating low dynamic