An Integrated Architectural Clock Implemented Memory Design Analysis


Received Jan 12, 2015 Revised Mar 28, 2015 Accepted Apr 22, 2015 Recently Low power custom memory design is the major issue for embedded designer. Micro wind and Xilinx simulator performs efficient cache simulation and high performances with low power consumption. SRAM efficiency analyzed with 6-T architecture design and analyzed the simulation performance… (More)


18 Figures and Tables