An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design

@article{Fang2007AnIL,
  title={An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design},
  author={Jia-Wei Fang and Chin-Hsiung Hsu and Yao-Wen Chang},
  journal={2007 44th ACM/IEEE Design Automation Conference},
  year={2007},
  pages={606-611}
}
The flip-chip package provides a high chip-density solution to the demand for more I/O pads of VLSI designs. In this paper, we present the first routing algorithm in the literature for the pre-assignment flip-chip routing problem with a pre-defined netlist among pads and wire-width and signal-skew considerations. Our algorithm is based on integer linear programming (ILP) and guarantees to find an optimal solution for the addressed problem. It adopts a two-stage technique of global routing… CONTINUE READING

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Key Quantitative Results

  • Without loss of the solution optimality, our reduction techniques can further prune the ILP variables (constraints) by 85.5% (98.0%) on average over a recent reduction technique.
  • Experimental results based on five real industry designs show that our router can achieve 100% routability and the optimal global-routing wirelength and satisfy all signal-skew constraints, under reasonable CPU times, while recent related work results in much inferior solution quality.
  • Without loss of the solution optimality, our reduction techniques can further prune the ILP variables (constraints) by 85.5% (98.0%) on average over a recent reduction technique.
  • Experimental results based on .ve real industry designs show that our router can achieve 100% routability and the optimal global-routing wirelength and satisfy all signal-skew constraints, under reasonable CPU times, while recent related work results in much inferior solution qual­ity.
  • In the second phase, bend minimization is performed under the 100% routabil­ity guarantee.
  • The experi­mental results show that our ILP based algorithm can achieve 100% routability and the optimal global-routing wirelength and satisfy all signal-skew constraints, under reasonable CPU times.
  • Experimental results have demonstrated that our router can achieve 100% routability and the optimal global-routing wire­length and satisfy all signal-skew constraints, under reasonable CPU times.

Citations

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Routing for chip-package-board co-design considering differential pairs

  • 2008 IEEE/ACM International Conference on Computer-Aided Design
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Recent research development in flip-chip routing

  • 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
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An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs

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On using SAT to ordered escape problems

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Ordered escape routing based on Boolean satisfiability

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Single layer differential group routing for flip-chip designs

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Ordered escape routing using network flow and optimization model

  • 2015 6th International Conference on Automation, Robotics and Applications (ICARA)
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