Corpus ID: 32301534

An Improved Tolerant Permanent Faults in FIFO Buffers of NOC Routers Using Bench Mark Circuits

@inproceedings{Kumar2016AnIT,
  title={An Improved Tolerant Permanent Faults in FIFO Buffers of NOC Routers Using Bench Mark Circuits},
  author={Rachapudi Deevan Kumar},
  year={2016}
}
  • Rachapudi Deevan Kumar
  • Published 2016
  • This router buffers during the operation in the field of short-encrypted hard faults NOC first in first out transparent testing technology in the development of the proposed on-line for this identity of faults. A model of the proposed algorithm to run the test periodically to prevent the accumulation of repetitive tests, the router technique involves be integrated into the channel interface and on-line testing has been performed with data traffic, such as synthetic self. The area has been… CONTINUE READING

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    SHOWING 1-10 OF 11 REFERENCES
    Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips
    • Kim Petersén, J. Öberg
    • Engineering, Computer Science
    • 2007 Design, Automation & Test in Europe Conference & Exhibition
    • 2007
    • 60
    • PDF
    Methodologies and algorithms for testing switch-based NoC interconnects
    • 61
    • PDF
    Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
    • 38
    Methods for fault tolerance in networks-on-chip
    • 177
    • Highly Influential
    • PDF
    A Cost-Effective Scheme for Network-on-Chip Router and Interconnect Testing
    • D. Xiang
    • Computer Science
    • 2013 22nd Asian Test Symposium
    • 2013
    • 15
    Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme
    • D. Xiang, Ye Zhang
    • Engineering, Computer Science
    • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
    • 2011
    • 46
    Route packets, not wires: on-chip interconnection networks
    • W. Dally, B. Towles
    • Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)
    • 2001
    • 2,495
    • Highly Influential
    Minimal-path fault-tolerant approach using connection-retaining structure in Networks-on-Chip
    • 46
    • PDF
    Parameter Variation Tolerance and Error Resiliency: New Design Paradigm for the Nanoscale Era
    • 182
    • Highly Influential
    • PDF
    Threshold-Based Mechanisms to Discriminate Transient from Intermittent Faults
    • 137
    • Highly Influential
    • PDF