An Improved Squaring Circuit for Binary Numbers

@inproceedings{Sethi2012AnIS,
  title={An Improved Squaring Circuit for Binary Numbers},
  author={Kabiraj Sethi},
  year={2012}
}
In this paper, a high speed squaring circuit for binary numbers is proposed. High speed Vedic multiplier is used for design of the proposed squaring circuit. The key to our success is that only one Vedic multiplier is used instead of four multipliers reported in the literature. In addition, one squaring circuit is used twice. Our proposed Squaring Circuit seems to have better performance in terms of speed. Keywords-Vedic mathematics; VLSI; binary multiplication; hardware design; VHDL. 

References

Publications referenced by this paper.
Showing 1-10 of 18 references

Gautam, “Performance Evaluation of Squaring Operation by Vedic Mathematics

  • S Prabha, Kasliwal, D.K.B.P. Patil
  • IETE Journal of Research,
  • 2011
Highly Influential
6 Excerpts

Computer Arithmetic Algorithms and Hardware Architectures

  • B. Parhami
  • 2nd ed, Oxford University Press, New York, 2010.
  • 2010
Highly Influential
4 Excerpts

High Speed Vedic Multiplier for Digital Signal Processors

  • R. Pushpangadan, V. Sukumaran, R.Innocent, D. Sasikumar, V. Sundar
  • IETE Journal of Research, vol.55, pp.282-286…
  • 2009
1 Excerpt

Vedic mathematics

  • Maharaja, J.S.S.B.K.T.
  • Motilal Banarsidass Publishers Pvt. Ltd, Delhi…
  • 2009
1 Excerpt

VLSI Implementation of Matrix- Diagonal Method of Binary Multiplication

  • P. Nair, D. Paranji, S. S. Rathod
  • Proc. of SPIT-IEEE Colloquium and Int Conf…
  • 2008
1 Excerpt

Similar Papers

Loading similar papers…