• Corpus ID: 212581671

An Implementation of Efficient Low Power VLSI Architecture for Image Compression System Using DCT and IDCT”

  title={An Implementation of Efficient Low Power VLSI Architecture for Image Compression System Using DCT and IDCT”},
  author={Sarita S Umadi and Gauri. D. Kulkarni},
Image compression is an important topic in digital world. It is the art of representing the information in a compact form. This project deals with the implementation of low power VLSI architecture for image compression system using DCT. Discrete Cosine Transform (DCT) constitutes a powerful tool in signal processing; the discrete cosine transform (DCT) is a technique for converting a signal into elementary frequency components. Discrete Cosine Transform (DCT) is the most widely used technique… 



A low-power, high-speed DCT architecture for image compression: Principle and implementation

  • M. JridiA. Alfalou
  • Computer Science
    2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip
  • 2010
A new design of low-power and high-speed Discrete Cosine Transform (DCT) for image compression to be implemented on Field Programmable Gate Arrays (FPGAs) is presented and a new technique based on Common Subexpression Elimination (CSE) is examined.

Low power DCT implementation using differential pixels for on-board satellite image processing

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The proposed implementation scheme does not require any multiplier as well as scaling compensation in the computation and the constant coefficient in the rotation blocks are represented in CSD and the multiplication is approximated by shift and add operation.

Image Compression Using the Discrete Cosine Transform

Some simple functions to compute the discrete cosine transform and how it is used for image compression are developed to illustrate the use of Mathematica in image processing and to provide the reader with the basic tools for further exploration of this subject.

Low power DCT using highly scalable multipliers

It is shown that using a scalable multiplier and dynamically reconfiguring the width of the multiplier leads to significant power savings (over 72%) with negligible degradation in decoded image quality.

Performance Evaluation of 4x4 DCT Algorithms for Low Power Wireless Applications

The paper compares the performance of 4 x 4 block based discrete cosine transforms with conventional 8 x 8 DCT on the basis of computation time and objective quality, based on PSNR (peak signal to noise ratio).

The JPEG still picture compression standard

The Baseline method has been by far the most widely implemented JPEG method to date, and is sufficient in its own right for a large number of applications.

Data Compression: The Complete Reference

Detailed descriptions and explanations of the most well-known and frequently used compression methods are covered in a self-contained fashion, with an accessible style and technical level for specialists and nonspecialists.

Fractions in the Canonical-Signed-Digit Number System

Canonical-signed-digit (CSD) coefficient representations lead to efficient add/subtract networks for hardwired DSP multiplies of two’s complement signals. CSD has always been considered a fixed-point

Practical fast 1D DCT algorithm with 11 multiplications,

  • 1989