An ILP-based automatic bus planner for dense PCBs

Abstract

Modern PCBs have to be routed manually since no EDA tools can successfully route these complex boards. An auto-router for PCBs would improve design productivity tremendously since each board takes about 2 months to route manually. This paper focuses on a major step in PCB routing called bus planning. In the bus planning problem, we need to simultaneously solve the bus decomposition, escape routing, layer assignment and global bus routing. This problem was partially addressed by Kong et al. in [3] where they only focused on the layer assignment and global bus routing, assuming bus decomposition and escape routing are given. In this paper, we present an ILP-based solution to the entire bus planning problem. We apply our bus planner to an industrial PCB (with over 7000 nets and 12 signal layers) which was previously successfully routed manually, and compare with a state-of-the-art industrial internal tool where the layer assignment and global bus routing are based on the algorithm in [3]. Our bus planner successfully routed 97.4% of all the nets. This is a huge improvement over the industrial tool which could only achieve 84.7% routing completion for this board.

DOI: 10.1109/ASPDAC.2013.6509593

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Cite this paper

@article{Wu2013AnIA, title={An ILP-based automatic bus planner for dense PCBs}, author={Pei-Ci Wu and Qiang Ma and Martin D. F. Wong}, journal={2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)}, year={2013}, pages={181-186} }