An IEEE 1149.1 Compliant Testability Architecture with Internal Scan

Abstract

This paper describes a testability architecture for VLSl devices which is IEEE 1149.1 compliant and includes extensions for partitionable internal scan chains. The architecture includes a fully synchronous scan cell library and an explicit synchronization barrier beween test clock synchronous logic and system clock synchronous logic. The explicit… (More)
DOI: 10.1109/ICCD.1992.276309

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Cite this paper

@inproceedings{Zak1992AnI1, title={An IEEE 1149.1 Compliant Testability Architecture with Internal Scan}, author={Robert C. Zak and Jeffrey V. Hill}, booktitle={ICCD}, year={1992} }