An FPGA prototype for the experimental evaluation of a multizone network cache

Abstract

Network routers rely on Content Addressable Memories (CAMs) to accelerate the process of looking up the next hop of a packet. We describe our implementation of a versatile prototype for a CAM. This prototype allows the empirical evaluation of the idea of caching lookup results in a multizone cache organized according to the length of the network prefix portion of the addresses. Implementing a cache in an FPGA efficiently required the design of a new cache replacement policy, the Bank Nth Chance policy. In this paper we present results from a functional simulator that allows the comparison of this new policy with existing ones such as LRU, FIFO and Second Chance. We have a complete and functional prototype with pipelined lookups implemented in a Xilinx Virtex 2000E device; we also report frequency of operation and occupation of the device.

DOI: 10.1145/968280.968341

Cite this paper

@inproceedings{Berube2004AnFP, title={An FPGA prototype for the experimental evaluation of a multizone network cache}, author={Paul Berube and Jos{\'e} Nelson Amaral and Mike H. MacGregor}, booktitle={FPGA}, year={2004} }