An FPGA implementation of a flexible architecture for H.263 video coding

@article{Garrido2002AnFI,
  title={An FPGA implementation of a flexible architecture for H.263 video coding},
  author={Mat{\'i}as J. Garrido and C{\'e}sar Sanz and Marcos Jim{\'e}nez and Juan M. Meneses},
  journal={2002 Digest of Technical Papers. International Conference on Consumer Electronics (IEEE Cat. No.02CH37300)},
  year={2002},
  pages={274-275}
}
In this paper the implementation of an H.263 base-line video coder on an FPGA-based platform is explained. The coder consists of a set of specialised processors for the main tasks (DCT, quantizations, motion estimation) and a RISC for the scheduling tasks. The design has been written in synthesizable Verilog and fully tested with hardware-software co-simulation using standard video sequences. Finally, the coder has been tested on a prototyping board with a RISC processor and an FPGA. 

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