An FPGA design for the Two-Band Fast Discrete Hartley Transform

Abstract

The discrete Hartley transform finds numerous applications in signal and image processing. An efficient Field Programmable Gate Array implementation for the 64-point Two-Band Fast Discrete Hartley Transform is proposed in this communication. The architecture requires 57 clock cycles to compute the 64-point Two-Band Fast Discrete Hartley Transform and… (More)
DOI: 10.1109/ISSPIT.2016.7886052

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