An FPGA based parameterisable system for discrete Hartley transforms implementation

@inproceedings{Amira2003AnFB,
  title={An FPGA based parameterisable system for discrete Hartley transforms implementation},
  author={Abbes Amira},
  booktitle={ICIP},
  year={2003}
}
Discrete Hartley Transforms (DHTs) are very important in many types of applications including image enhancement, acoustics, optics, telecommunications and speech signal processing. Two novel architectures for computing DHTs using both systolic architecture and distributed arithmetic design methodologies are presented in this paper. The first approach uses the Modified Booth-encoder-Wallace trees Multiplication (MBWM) algorithm for a systolic architecture implementation. The second approach is… CONTINUE READING

Citations

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