An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking

@article{Szplet2010AnFT,
  title={An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking},
  author={R. Szplet and K. Klepacki},
  journal={IEEE Transactions on Instrumentation and Measurement},
  year={2010},
  volume={59},
  pages={1663-1670}
}
We present the design and test results of a new time-to-digital converter based on the cyclic pulse shrinking method and implemented in a field-programmable gate array (FPGA) device. The pulse shrinking is realized in a loop containing two complementary delay lines. The first line shrinks, and the second line stretches the duration time of a circulating… CONTINUE READING