• Corpus ID: 86984

An FPGA Implementation of the Digital IF Processor

  title={An FPGA Implementation of the Digital IF Processor},
  author={Grant A. Hampson},
This document describes the simulation and FPGA implementation of the IIP Radiometer Digital IF Section described in [1]. The digital IF processor presented here is a slightly different to that of [1]. The digital IF processor implemented here is illustrated in Figure 1 where there are four distinct sections; namely demultiplex, FS/4 down conversion, filtering and FS/4 up conversion. The structure differs by keeping the FS/4 down conversion and FIR filter coefficients separate. In the original… 

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