An FPGA Implementation of Explicit-State Model Checking

  title={An FPGA Implementation of Explicit-State Model Checking},
  author={Mary Ellen Fuess and Miriam Leeser and Tim Leonard},
  journal={2008 16th International Symposium on Field-Programmable Custom Computing Machines},
We present PHAST, a pipelined hardware accelerated explicit-state model checker. The algorithms and methodologies used to perform the state checking in PHAST are based on the Mur¿ verifier, developed at Stanford University. Mur¿ has been used to verify hardware and protocols, cache coherency protocols in particular. Mur¿ is used in industry due to its success in finding errors in real designs. Until now, Mur¿ and other model checkers have been solely performed in software. PHAST takes advantage… CONTINUE READING


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