An Energy and Performance Exploration of Network-on-Chip Architectures

@article{Banerjee2009AnEA,
  title={An Energy and Performance Exploration of Network-on-Chip Architectures},
  author={Arnab Banerjee and Pascal T. Wolkotte and Robert D. Mullins and Simon W. Moore and Gerard J. M. Smit},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2009},
  volume={17},
  pages={319-329}
}
In this paper, we explore the designs of a circuit-switched router, a wormhole router, a quality-of-service (QoS) supporting virtual channel router and a speculative virtual channel router and accurately evaluate the energy-performance tradeoffs they offer. Power results from the designs placed and routed in a 90-nm CMOS process show that all the architectures dissipate significant idle state power. The additional energy required to route a packet through the router is then shown to be… CONTINUE READING

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