An Energy-Efficient Clustered Superscalar Processor

Abstract

Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speedcritical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation. key words: low power architecture, energy reduction, clustered processors, dual-voltage pipeline, critical path prediction

DOI: 10.1093/ietele/e88-c.4.544

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Cite this paper

@article{Sato2005AnEC, title={An Energy-Efficient Clustered Superscalar Processor}, author={Toshinori Sato and Akihiro Chiyonobu}, journal={IEICE Transactions}, year={2005}, volume={88-C}, pages={544-551} }