• Corpus ID: 18508888

An Energy Conservation DVFS Algorithm for the Android Operating System

  title={An Energy Conservation DVFS Algorithm for the Android Operating System},
  author={Wen-Yew Liang and Po-Ting Lai and Che Wun Chiou},
Typically, when a user wishes to minimise the energy consumption for an application running on a handheld device, he/she may choose to set the processor speed to its slowest level. However, our study indicated that due to the processes involved in memory accesses, decreasing the CPU frequency may not always reduce the energy consumption. A critical speed has been defined as the CPU frequency, at which energy consumption can be minimised for a program. It can be used when the user wants to… 

Schedule-aware DVFS Algorithm on Android Platforms for Energy Minimization

This paper proposes a simple but novel DVFS algorithm on Android based smartphones that uses the information from operating system scheduler and process history table which is made by the proposed method and is superior in terms of energy saving.

A Middleware for Power Management in Multicore Smartphones

Three new power-aware scheduling algorithms that dynamically schedule optimal number of cores as well as dynamically adjust the voltage frequency of each online core are proposed to achieve the best tradeoff between power consumption, application performance and user experience under the current context.

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An approach to tuning CPU DVFS Ondemand governor at the Android application level that allows better balance between the two aspects and allows users to tune their governor policies dynamically and without having to reinstall custom Android OS for their phones.

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A study of power consumption of multithreading Android applications running only Java applications against Android running computationally complex sections of code in intermediate language, such as C using JNI to help have application development strategies aimed at saving energy.

A Power-Saving Technique for the OSGi Platform

The results show that this approach can achieve real power-savingiency for the OSGi platform, in which the power consumption is significantly re- duced and the performance remains highly competitive, compared with the other power- saving techniques.

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This paper proposes a scheme called SpeedControl which jointly manages application scheduling, CPU speed control and wireless interface selection, and is shown to be near-optimal in that it tends to minimize energy consumption for given delay constraints.

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An approximation equation based on the correlation of the memory access rate and the critical speed for the minimum energy consumption is conducted for frequency and voltage prediction and an MA-DVFS (memory-aware DVFS) algorithm is proposed, realized in the Linux kernel.

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A systematic approach to building platform-specific but workload-independent performance and power models that can accurately predict the energy use of a wide class of applications and is highly responsive to changes in the application behaviour.

A Dual Speed Approach to Workload-Aware Voltage Scaling

This paper experimentally evaluates the DVS capabilities of a mobile platform based on the XScale PXA255 processor and introduces a novel DVS approach, called Loadaware Dual-speed Dynamic Voltage Scaling (LD-DVS), that increases the obtainable energy savings.

Accurate Run-Time Prediction of Performance Degradation under Frequency Scaling

This paper presents a methodology, based on off-line hardware characterisation and runtime workload characterisation, for the generation of an execution time model that provides a highly accurate prediction of performance at arbitrary frequency settings and that the models can be used to implement operating-system level dynamic voltage and frequency scaling schemes for embedded systems.

Dynamic voltage and frequency scaling based on workload decomposition

  • Kihwan ChoiR. SomaMassoud Pedram
  • Computer Science
    Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)
  • 2004
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Power prediction for Intel XScale processors using performance monitoring unit events

A first-order, linear power estimation model that uses performance counters to estimate run-time CPU and memory power consumption of the Intel PXA255 processor that can serve as a foundation for intelligent, poweraware embedded systems that dynamically adapt to the device’s power consumption is demonstrated.

Workload-Aware Dual-Speed Dynamic Voltage Scaling

  • D. RajanR. ZuckC. Poellabauer
  • Computer Science
    12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06)
  • 2006
This work introduces an online approach to dual-speed DVS that formulates a model for speed selection based on the workload characteristics of the current task set and computes a frequency pair that yields the best possible energy savings for a given taskset and workload.

Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times

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MiBench: A free, commercially representative embedded benchmark suite

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Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems

  • R. JejurikarRajesh K. Gupta
  • Computer Science
    Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758)
  • 2004
This work presents an algorithm to compute task slowdown factors based on the contribution of the processor leakage and standby energy consumption of the resources in the system, and shows that the scheduling approach minimizes the total static and dynamic energy consume of the systemwide resources.