An Efficient VLSI Design Approach to Reduce Static Power using Variable Body Biasing

@inproceedings{Chowdhury2012AnEV,
  title={An Efficient VLSI Design Approach to Reduce Static Power using Variable Body Biasing},
  author={Asif Jahangir Chowdhury and Shahriar Rizwan and M. S. Islam},
  year={2012}
}
In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these… CONTINUE READING

Similar Papers

Loading similar papers…