An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA

@article{Fiser2008AnEM,
  title={An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA},
  author={Petr Fiser and Pavel Kubal{\'i}k and Hana Kubatova},
  journal={2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools},
  year={2008},
  pages={96-99}
}
We propose a method to efficiently design a "parity generator", which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designed by duplicating the original circuit, XOR-ing given groups of its outputs and resynthesizing the whole circuit. The resulting circuitry is mostly smaller than the original circuit… CONTINUE READING