An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding

This paper presents an efficient multi-standard low-density parity-check (LDPC) decoder architecture using a shuffled decoding algorithm, where variable nodes are divided into several groups. In order to provide sufficient memory bandwidth without the need for using registers, a FIFO-based check-mode memory, which dominates the decoder area, is used. Since… CONTINUE READING