An Efficient Deterministic Test Pattern Compaction Scheme Using Modified IC Scan Chain


In this paper, we propose a new scheme for Built-In Self-Test (BIST) that uses an LFSR obtained by adding feedback loops to the IC boundary scan chain. This LFSR first generates random patterns to cover easy-to-test faults and after the random testing phase it is partially loaded with seeds to generate deterministic vectors for hard-to-test faults. The… (More)


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