An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs

@article{Girard2006AnEB,
  title={An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs},
  author={Patrick Girard and Olivier H{\'e}ron and Serge Pravossoudovitch and Michel Renovell},
  journal={J. Electronic Testing},
  year={2006},
  volume={22},
  pages={161-172}
}