An Efficient 16-Bit Multiplier based on Booth Algorithm

Abstract

Multipliers are key components of many high performance systems such as microprocessors, digital signal processors, etc. Optimizing the speed and area of the multiplier is major design issue which is usually conflicting constraint so that improving speed results mostly in bigger areas. A VHDL designed architecture based on booth multiplication algorithm is proposed which not only optimize speed but also efficient on energy use.

Cite this paper

@inproceedings{Zamin2012AnE1, title={An Efficient 16-Bit Multiplier based on Booth Algorithm}, author={Muhammad Zamin and Ali Khan and Hussain Saleem and Shiraz Afzal and Jawed Naseem}, year={2012} }