An Automatic Controller Extractor for HDL Descriptions at the RTL

  title={An Automatic Controller Extractor for HDL Descriptions at the RTL},
  author={Chien-Nan Jimmy Liu and Jing-Yang Jou},
  journal={IEEE Design & Test of Computers},
ern circuit designs, verification has become the major bottleneck in the entire design process.1 To cope with the exponential state-space growth, researchers have proposed some techniques2,3 to reduce this state space in functional verification at the register transfer level (RTL). Because most design errors are related to the design’s control part, one possible solution is to separate the data paths from the controllers and verify the control part only. However, in the proposed techniques, the… CONTINUE READING


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