An Automatic Controller Extractor for HDL Descriptions at the RTL

@article{Liu2000AnAC,
  title={An Automatic Controller Extractor for HDL Descriptions at the RTL},
  author={Chien-Nan Jimmy Liu and Jing-Yang Jou},
  journal={IEEE Design & Test of Computers},
  year={2000},
  volume={17},
  pages={72-77}
}
ern circuit designs, verification has become the major bottleneck in the entire design process.1 To cope with the exponential state-space growth, researchers have proposed some techniques2,3 to reduce this state space in functional verification at the register transfer level (RTL). Because most design errors are related to the design’s control part, one possible solution is to separate the data paths from the controllers and verify the control part only. However, in the proposed techniques, the… CONTINUE READING

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References

Publications referenced by this paper.
Showing 1-8 of 8 references

Practical FSM Analysis for Verilog,

  • T.-H. Wang, T. Edsall
  • Proc. IEEE Int’l Verilog HDL Conf. and VHDL Users…
  • 1998

New Hybrid Methodology for Power Estimation,

  • D. I. Cheng
  • Proc. 33rd ACM/IEEE Design Automation Conf.,
  • 1996

R . C . Ho and M . A . Horowitz , “ Validation Coverage Analysis for Complex Digital Designs

  • J. A. Abraham Moundanos, Y. V. Hoskote
  • Proc . IEEE / ACM Int ’ l Conf . Computer - Aided…
  • 1996

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