An Asymptotically Scalable Superscalar Microarchitecture or How I Learned to Stop Worrying and Love Out-of-Order Executiona

Abstract

Today’s superscalar processors rename registers, bypass registers, checkpoint state so that they can recover from speculative execution, check for dependencies, allocate execution units, and access multi-ported register files. The circuits employed are complex and irregular, requiring much effort and ingenuity to implement well. Furthermore, the delays… (More)

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