• Computer Science
  • Published 2012

An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term

@inproceedings{Wey2012AnAC,
  title={An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term},
  author={I-Chyn Wey and Cheng-Chen Ho and Yi-Sheng Lin and Chien-Chang Peng},
  year={2012}
}
 Abstract—In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select… CONTINUE READING

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