An Analog VLSI Chip with AsynchronousInterface for Auditory Feature


An Analog VLSI Chip with Asynchronous Interface for Auditory Feature Extraction Nagendra Kumar, Wolfgang Himmelbauer, Gert Cauwenberghs, Andreas G. Andreou Center for Language and Speech Processing Johns Hopkins University, Baltimore MD 21218, USA. Abstract|We describe the architecture and circuit implementation of an analog VLSI feature extraction chip that has an asynchronous digital interface and is designed to serve as an auditory based front-end for a digit recognition system. The single chip system encodes signal energies and level crossing time intervals of frequency components in a cochlear lter bank. The chip has been fabricated in a 1.2 m n-well, double polysilicon double metal CMOS process and it is fully functional. Power consumption when operated from 5 Volt supply is only a few milliwatts.

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@inproceedings{Kumar1998AnAV, title={An Analog VLSI Chip with AsynchronousInterface for Auditory Feature}, author={Nagendra Kumar and Wolfgang Himmelbauer and Gert Cauwenberghs and Andreas G. Andreou}, year={1998} }