An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency

@article{Gao2016AnAP,
  title={An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency},
  author={Junfeng Gao and Guangjun Li and Letian Huang and Qiang Li},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2016},
  volume={63},
  pages={341-345}
}
A new pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) structure without residue amplifier and timing-interleaving is presented in this brief. Two redistribution digital-to-analog converters (DACs) and comparators are adopted in two stages, with DAC1 for most significant bit (MSB) comparisons and DAC2 for least significant bit (LSB) comparisons. The previous sampled signal is transferred from DAC1 to DAC2 through charge sharing so that previous LSB conversions… CONTINUE READING
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