An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits

  title={An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits},
  author={Yi-Chieh Huang and Ping-Ying Wang and Shen-Iuan Liu},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
An all-digital on-chip jitter tolerance measurement technique for clock/data recovery (CDR) circuits is presented. A 6-Gbps CDR circuit with this proposed technique is realized in a 90-nm CMOS process. The measured jitter tolerance by using the testing equipment and the proposed technique correlate within 13 % in the frequency range of 178 kHz ~ 11.3 MHz. The measured peak-to-peak data and clock jitters are 15.56 and 13.3 ps. The power of the CDR circuit is 44.4 mW at a supply voltage of 1.2 V. 


Publications referenced by this paper.
Showing 1-9 of 9 references

A 3.2 Gb/s CDR using semi-blind oversampling to achieve high jitter tolerance

  • M. V. Ierssel, A. Sheikholeslami, H. Tamura, W. W. Walker
  • IEEE J. Solid-State Circuits, vol. 42, no. 10, pp…
  • 2007

Design of Integrated Circuits for Optical Communications

  • B. Razavi
  • Int. ed. New York: McGraw-Hill,
  • 2002
1 Excerpt

Clock recovery from random binary data

  • J.D.H. Alexander
  • Electron. Lett., vol. 11, no. 22, pp. 541–542…
  • 1975
1 Excerpt

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