An All-Digital Fast-Locking Programmable DLL-Based Clock Generator

@article{Liang2008AnAF,
  title={An All-Digital Fast-Locking Programmable DLL-Based Clock Generator},
  author={Chuan-Kang Liang and Rong-Jyi Yang and Shen-Iuan Liu},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2008},
  volume={55},
  pages={361-369}
}
An all-digital fast-locking programmable DLL-based clock generator is presented. By resetting the output clock every two input clock periods, the initial minimal delay constraint in the conventional architecture is eliminated. Compared with the previous work, the short locking time is also achieved. The proposed circuit has been fabricated in 0.35-mum CMOS process and occupies the active area of 0.216 mm2. The clock multiplication ratio is programmed from 2 to 15. The frequency ranges of the… CONTINUE READING
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