An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors


The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the capacity of shared last-level caches efficiently and to allow for a short access time, proposed non-uniform cache architectures (NUCAs) are organized into per-core partitions. If a… (More)
DOI: 10.1109/HPCA.2007.346180


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