An Accurate Worst Case Timing Analysis for RISC Processors

  title={An Accurate Worst Case Timing Analysis for RISC Processors},
  author={Sung-Soo Lim and Young Hyun Bae and Gyu Tae Jang and Byung-Do Rhee and Sang Lyul Min and Chang Yun Park and Heonshik Shin and Kunsoo Park and Soo-Mook Moon and Chong-Sang Kim},
  journal={IEEE Trans. Software Eng.},
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Publications referenced by this paper.
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High-Level Timing Speci cation of Instruction-Level Parallel Processors,

  • E. Harcourt, J. Mauney, T. Cook
  • Tech. Rep. TR-93-18,
  • 1993
Highly Influential
6 Excerpts

Static Analysis of Cache Performance for Real-Time Programming,"Master's

  • J. Rawat
  • Iowa State University,
  • 1993
Highly Influential
4 Excerpts

Data Cache Analysis Techniques for Real-Time Systems," Master's thesis, Seoul

  • Y. H. Bae
  • National University,
  • 1995
2 Excerpts

Instruction Cache and Pipelining Analysis Technique for Real-Time Systems," Mas- ter's thesis, Seoul

  • S.-S. Lim
  • National University,
  • 1995
2 Excerpts

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