An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists

@article{Baumgartner2003AnAA,
  title={An Abstraction Algorithm for the Verification of Level-Sensitive Latch-Based Netlists},
  author={Jason Baumgartner and Tamir Heyman and Vigyan Singhal and Adnan Aziz},
  journal={Formal Methods in System Design},
  year={2003},
  volume={23},
  pages={39-65}
}
High-performance hardware designs often intersperse comb inational logic freely between level-sensitive latch layers (wherei n ach layer is transparent during only one clock phase), rather than utilizing mast erlave latch pairs with no combinational logic between. While such designs may generally achieve much faster clock speeds, this design style poses a challeng e to verification. In particular, unless the k-phase netlist N is abstracted to a full-cycle register-based netlistN 0, verification… CONTINUE READING
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