An ASIC for fast grey-scale dilation

The design and VLSI implementation of a new ASIC which performs the operation of grey-scale dilation using both image and structuring element threshold decomposition is presented in this paper. The minimum rate of external operations of this ASIC is 30 MPix/sec and it can handle 3 x 3 pixel images and structuring elements of up to 4-bit resolution. The high… CONTINUE READING