An ADPLL circuit using a DDPS for genlock applications

@article{Calbaza2004AnAC,
  title={An ADPLL circuit using a DDPS for genlock applications},
  author={Dorin Emil Calbaza and Ioan Cordos and Nigel Seth-Smith and Yvon Savaria},
  journal={2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)},
  year={2004},
  volume={4},
  pages={IV-569}
}
This paper presents a fully programmable All-Digital PLL (ADPLL) circuit that is able to synchronize any frequency between 12 MHz and 200 MHz, with a frequency between 24 Hz and 100 MHz. This ADPLL circuit uses a Direct Digital Period Synthesizer as a digitally controlled oscillator. The measured jitter at the output is between 184 and 274 ps (depending on control parameters). The circuit is implemented in 0.18 /spl mu/m CMOS technology and dissipates 50 mW when running at 150 MHz. 

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