An 8GHz floating-point multiply

@article{Belluomini2005An8F,
  title={An 8GHz floating-point multiply},
  author={Wendy Belluomini and Damir Jamsek and August Martin and Chandler McDowell and Robert Montoye and Thien Dinh Nguyen and Hung Q. Ngo and J. Sawada and Ivan Vo and Rupa Datta},
  journal={ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.},
  year={2005},
  pages={374-604 Vol. 1}
}
The implementation of the mantissa portion of a floating-point multiply (54/spl times/54b) is described. The 0.124mm/sup 2/ multiplier is implemented using limited switch dynamic logic and operates at speeds up to 8GHz in a 90nm SOI technology. The multiplier dissipates between 150mW and 1.8W as it scales between 2GHz and 8GHz. 

From This Paper

Topics from this paper.

Citations

Publications citing this paper.
Showing 1-6 of 6 extracted citations

References

Publications referenced by this paper.
Showing 1-3 of 3 references

A 4Ghz 64b Integer Execution ALU with Dual Supply voltages in 90nm CMOS,

S. Mathew
ISSCC Dig. Tech. Papers, pp.162-163, • 2004
View 2 Excerpts

Low-voltage-swing logic circuits for a 7GHz x86 integer core

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519) • 2004
View 2 Excerpts

A double precision floating point multiply

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. • 2003
View 6 Excerpts

Similar Papers

Loading similar papers…