An 8GHz floating-point multiply

  title={An 8GHz floating-point multiply},
  author={Wendy Belluomini and Damir Jamsek and August Martin and Chandler McDowell and Robert Montoye and Thien Dinh Nguyen and Hung Q. Ngo and J. Sawada and Ivan Vo and Rupa Datta},
  journal={ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.},
  pages={374-604 Vol. 1}
The implementation of the mantissa portion of a floating-point multiply (54/spl times/54b) is described. The 0.124mm/sup 2/ multiplier is implemented using limited switch dynamic logic and operates at speeds up to 8GHz in a 90nm SOI technology. The multiplier dissipates between 150mW and 1.8W as it scales between 2GHz and 8GHz. 

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