An 860-Mb/s (8158,7136) Low-Density Parity-Check Encoder

@article{Miles2006An8,
  title={An 860-Mb/s (8158,7136) Low-Density Parity-Check Encoder},
  author={L. Miles and J. W. Gambles and G. Maki and W E Ryan and S. Whitaker},
  journal={IEEE Journal of Solid-State Circuits},
  year={2006},
  volume={41},
  pages={1686-1691}
}
Low-density parity-check codes achieve coding performance which approaches the Shannon limit. An (8158,7136) encoder was implemented in a five-metal, 0.25-mum CMOS process. Use of generator polynomial reconstruction, partial product multiplication and functional sharing in the parity register results in a highly efficient design. Only 1492 flip-flops along with a programmable 21-bit look-ahead scheme are used to achieve an 860-Mb/s data throughput for this rate 7/8 LDPC code. A comparable two… CONTINUE READING