An 8192-bit electrically alterable ROM employing a one-transistor cell with floating gate

Abstract

Describes a fully decoded, TTL compatible, electrically alterable, 8-kbit MOS ROM using a two-level n-channel polysilicon gate process. The memory cell consists of a single transistor with stacked gate structure where the floating gate covers only one part of the channel and is extended to an erase overlap of the source diffusion region off the channel… (More)

Topics

11 Figures and Tables