An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

@article{Ihm2007An84,
  title={An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion},
  author={Jeong-Don Ihm and Seung-Jun Bae and Kwang-Il Park and Ho-Young Song and Woo-Jin Lee and Hyun-Jin Kim and Kyoung-Ho Kim and Ho-Kyung Lee and Min-Sang Park and Sam-Young Bang and Mi-Jin Lee and Gil-Shin Moon and Young-Wook Jang and Suk-Won Hwang and Young-Chul Cho and Sang-Jun Hwang and Dae-Hyun Kim and Ji-Hoon Lim and Jae-Sung Kim and Su-Jin Park and Ok-Joo Park and Se-Mi Yang and Jin-yong Choi and Young-Wook Kim and Hyun-Kyu Lee and Sunghoon Kim and Seong-Jin Jang and Young-Hyun Jun and Soo-In Cho},
  journal={2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers},
  year={2007},
  pages={492-617}
}
A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with an analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21 ps and voltage fluctuation by 68mV. A dual duty-cycle corrector is proposed to average duty error, and tuning is added to the auto-calibration of driver and termination impedance. 

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