An 800MHz star-connected on-chip network for application to systems on a chip

@article{Lee2003An8S,
  title={An 800MHz star-connected on-chip network for application to systems on a chip},
  author={Se-Joong Lee and Seong-Jun Song and Kangmin Lee and Jeong-Ho Woo and Sang-Hoon Kim and Byeong-Gyu Nam and Hoi-Jun Yoo},
  journal={2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.},
  year={2003},
  pages={468-469 vol.1}
}
A 10.8/spl times/6.0mm/sup 2/ prototype chip is implemented with a star-connected on-chip network. The chip consists of a PLL, 1KB SRAM, two 2/spl times/2 crossbar switches, Up/Down-Samplers, two off-chip gateways, and synchronizers. The on-chip network contains 81k transistors, dissipates 264mW at 2.3V and 800MHz, and provides 1.6GB/s per port and 12.8GB/s aggregated bandwidth, supporting plesiochronous communication without global synchronization. 
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