An 800-MHz embedded DRAM with a concurrent refresh mode

  title={An 800-MHz embedded DRAM with a concurrent refresh mode},
  author={Toshiaki Kirihata and P. Parries and Daniel Hanson and Hoki Kim and John Golz and Gregory Fredeman and R. Rajeevakumar and John Griesemer and Norman Robson and Alberto Cestero and B. Khan and Geng Wang and Matthew R. Wordeman and Subramanian S. Iyer},
  journal={IEEE Journal of Solid-State Circuits},
An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier… CONTINUE READING


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Publications referenced by this paper.

A 312 MHz 16 Mb random-cycle embedded DRAM macro with 73 mW power-down mode for mobile applications

  • F. Morishita, I. Hayashi, +8 authors K. Arimoto
  • IEEE ISSCC Dig. Tech. Papers, , pp. 202–203.
  • 2004
1 Excerpt

An 800 MHz embedded DRAM with a concurrent refresh mode

  • T. Kirihata, P. Parries, +9 authors S. Iyer
  • IEEE ISSCC Dig. Tech. Papers, , pp. 206–207.
  • 2004
1 Excerpt

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