An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

@article{Bae2008An8N,
  title={An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion},
  author={Seung-Jun Bae and Kwang-Il Park and Jeong-Don Ihm and Ho-Young Song and Woo-Jin Lee and Hyun-Jin Kim and Kyoung-Ho Kim and Yoon-Sik Park and Min-Sang Park and Hong-Kyong Lee and Sam-Young Bang and Gil-Shin Moon and Seok-won Hwang and Young-Chul Cho and Sang-Jun Hwang and Dae-Hyun Kim and Ji-Hoon Lim and Jae-Sung Kim and Sung-Hoon Kim and Seong-Jin Jang and Joo Sun Choi and Young-Hyun Jun and Kinam Kim and Soo-In Cho},
  journal={IEEE Journal of Solid-State Circuits},
  year={2008},
  volume={43},
  pages={121-131}
}
4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/O, power supply noise, and crosstalk. Both DBI AC and DC modes are combined to a single circuit by eliminating the feedback path of a conventional DBI AC circuit while achieving high-speed operation. The proposed DBI circuit uses an analog majority… CONTINUE READING

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