An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS

@article{Hsu2005An8D,
  title={An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS},
  author={Steven Hsu and Amit Agarwal and Kaushik Roy and Ram Krishnamurthy and Shekhar Y. Borkar},
  journal={ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.},
  year={2005},
  pages={103-106}
}
In high performance microprocessors, integer execution cores are one of the hottest thermal spots and peak current/power delivery limiters. This paper describes a dual-supply and dual-threshold optimized 32-bit integer execution ALU and register file loop for 8.3GHz operation in 1.2V, 90nm CMOS technology. Aggressive supply/threshold scaling on the ALU and nominal supply/threshold on the register file enables up to 25% peak energy reduction without sacrificing performance or array bit-cells… CONTINUE READING
4 Citations
0 References
Similar Papers

Citations

Publications citing this paper.

Similar Papers

Loading similar papers…