An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

@article{Chaturvedi2013An8B,
  title={An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording},
  author={Vikram Chaturvedi and T. Anand and B. Amrutur},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2013},
  volume={21},
  pages={2034-2044}
}
  • Vikram Chaturvedi, T. Anand, B. Amrutur
  • Published 2013
  • Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An… CONTINUE READING
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    References

    SHOWING 1-10 OF 31 REFERENCES
    An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes
    • 310
    • PDF
    A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
    • 822
    • PDF
    500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC
    • 294
    • Highly Influential
    • PDF
    A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
    • 478
    • Highly Influential
    • PDF
    A 8-bit 500-KS/s low power SAR ADC for bio-medical applications
    • 149
    A 1-V 60-µW 16-channel interface chip for implantable neural recording
    • 45
    A Low-Power 32-Channel Digitally Programmable Neural Recording Integrated Circuit
    • 135
    • PDF
    Adaptive Resolution ADC Array for an Implantable Neural Sensor
    • 49
    • PDF
    A 128-Channel 6 mW Wireless Neural Recording IC With Spike Feature Extraction and UWB Transmitter
    • 343
    • Highly Influential
    • PDF
    A low-power low-noise CMOS amplifier for neural recording applications
    • 1,057