An 8-Point IDCT Computing Resource Implemented on a TriMedia / CPU 64 Reconfigurable Functional Unit

@inproceedings{Sima2001An8I,
  title={An 8-Point IDCT Computing Resource Implemented on a TriMedia / CPU 64 Reconfigurable Functional Unit},
  author={Mihai Sima and Sorin Dan Cotofana and Jos T. J. van Eijndhoven and Stamatis Vassiliadis},
  year={2001}
}
This paper presents the implementation of an 8-point Inverse Discrete Cosine Transform (IDCT) computing resource on a TriMedia/CPU64 FPGA-based Reconfigurable Functional Unit (RFU). TriMedia/CPU64 is a 64-bit 5 issue-slot VLIW processor launching a long instruction every clock cycle. The RFU consists mainly of an FPGA core, and is embedded into the TriMedia as any other hardwired functional unit, i.e., it receives instructions from the instruction decoder, reads its input arguments from and… CONTINUE READING
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