An 8-Bit 250MSPS Modified Two-Step ADC

@article{Ning2006An82,
  title={An 8-Bit 250MSPS Modified Two-Step ADC},
  author={Ning Ning and Long Fan and Shuang-yi Wu and Yuan Liu and Guo-qing Liu and Qi Yu and Mo-hua Yang},
  journal={2006 International Conference on Communications, Circuits and Systems},
  year={2006},
  volume={4},
  pages={2197-2200}
}
Based on conventional two-step ADC principle, an 8-bit 250MSPS modified two-step ADC is proposed to reduce power dissipation. It is realized by applying triple-stage comparison for the number reduction of comparators, substituting new reference region selecting logic (RRSL) blocks for sub-DACs and adding sample/hold (S/H) circuit to replace residue amplifier. Simulated with SMIC O.35 mum/3.3 V AMS Si-CMOS process models, the results are shown that on the condition of realizing 250MSPS, the ADC… CONTINUE READING
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A 2.5-V 10-b Beijing

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