An 18 ns CMOS/SOS 4K static RAM

@article{Isobe1981An1N,
  title={An 18 ns CMOS/SOS 4K static RAM},
  author={Mitsuo Isobe and Y. Uchida and Kenji Maeguchi and Tohru Mochizuki and M. Kimura and Hiroshi Hatano and Yoshihisa Mizutani and Hiroyuki Tango},
  journal={IEEE Journal of Solid-State Circuits},
  year={1981},
  volume={16},
  pages={460-465}
}
A high-speed CMOS/SOS 4K word/spl times/1 bit static RAM is described. The RAM features a MoSi/SUB 2/ gate CMOS/SOS technology with 2 /spl mu/m gate length and 500 /spl Aring/ thick gate oxide. Performance advantage of SOS over bulk is discussed for the scaled-down MOS LSI with 1-2 /spl mu/m gate. A standard 6-transistor CMOS cell and a two-stage sense amplifier scheme are utilized. In spite of the rather conservative 3.5 /spl mu/m design rule except for the 2 /spl mu/m gate length, the cell… 
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